Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, these activities involve information processing with demands for greater performance and functionality increases. Pipelining the operations is one approach often utilized to increase performance. However, infrequent operations requiring relatively long periods of time to execute typically have a disproportionate adverse impact on the overall performance of traditional pipeline approaches.
Numerous electronic devices include processors that operate by executing programs comprising a series of instructions. These programs and their series of instructions are typically referred to as software. Software instructions include directions that guide processor device functions in the performance of useful tasks. The utility a processor device provides often depends upon the speed and efficiency at which instructions included in a software program are executed. Traditionally, tasks are performed in a serial manner in which one operation is performed and then the next operation is performed, one after another in a linear fashion. A purely sequential system typically requires a lot more time to complete a series of operations since one operation is not performed until the preceding operation is completed. Some traditional systems attempt to increase speed with pipelining.
Pipelining typically involves dividing operations associated with an instruction into stages and “overlapping” of instruction stage processing in an attempt allow “parallel” processing in which operations associated with one instruction are begun before the completion of operations from a previous instruction. For example, numerous traditional pipeline techniques include a fetch stage, decode stage, execute stage, and write stage. Pipelining is utilized by a variety of different applications. For example, there are a number of stages or processes included in a typical graphics pipeline and various manipulations of pixel data are implemented at each stage in the pipeline. These manipulations often involve numerous computational processes some of which are completed relatively quickly and others take a relatively long time to complete. The speed at which at which images are rendered in typical graphics systems is often critical to proper presentation of the information. Slow rendering rates often cause undesirable choppy or “jerky” presentations which usually results in a user experience that is non-immersive and unpleasant.
Conventional attempts at addressing pipeline timing are usually inefficient and/or resource intensive. In traditional pipelines, pipeline stage cycles are set at a fixed time corresponding to the slowest operation execution time. For example, each pipeline stage cycle is set to be equal to execution operations that take the longest period of time, even though the majority of execution operations can be performed faster. This approach tends to be relatively simplistic but tends to slow down the throughput of whole device. Some traditional pipeline systems attempt to address pipeline cycle time by adding hardware resources to speed up the pipeline which increases cost. Other traditional pipeline systems attempt to break slow paths down by adding another pipeline phase or cycle. In these systems, slow operations (e.g., a multiply) might take two cycles instead of one. However, these approaches also add two cycles to every operation or require sophisticated tracking to know that results of some execution operations can not be used until two cycles later.
Attempts have been made at self-timed logic to speed up pipelines. However, these attempts typically end up consuming more power and typically take longer to complete operations. In addition, trying to analyze and test self-timed logic is very complicated and resource intensive. Normal tools usually look at differences between two registers (e.g., the registers are gate keepers) for results at a particular time and what happens in one clock cycle is analyzed. However, in self-timed circuits there is usually a domino effect in that something that happens in one part of the chip feeds back and forth with other parts of the chip. This means numerous register results have to be analyzed at the same time when a chip is tested and analyzed.